march 2013 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 www.fairchildsemi.com 1 FDMA1430JP integrated p-channel powertrench ? mosfet and bjt FDMA1430JP integrated p-channel powertrench ? mosfet and bjt -30 v, -2.9 a, 90 m features ? max r ds(on) = 90 m at v gs = -4.5 v, i d = -2.9 a ? max r ds(on) = 130 m at v gs = -2.5 v, i d = -2.6 a ? max r ds(on) = 170 m at v gs = -1.8 v, i d = -1.7 a ? max r ds(on) = 240 m at v gs = -1.5 v, i d = -1 a ? low profile - 0.8 mm maximum - in the new package microfet 2x2 ? hbm esd protection level > 2 kv typical (note 3) ? rohs compliant general description this device is designed specific ally as a single package solution for loadswitching in cellular han dset and other ultra-portable applications. it features a 50 v npn bjt and a 30 v p-ch trench mosfet in the space saving micr ofet 2x2 package that offers exceptional thermal performance for it's physical size and is well suited to linear mode applications. application ? loadswitching ebd s cg pin 1 cd g e b d c s microfet 2x2 top bottom maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage -30 v v gs gate to source voltage 8 v i d drain current -continuous t a = 25c (note 1a) -2.9 a -pulsed -12 v cbo collector-base voltage (note 4) 50 v v ceo collector-emitter voltage (note 5) 50 v v ebo emitter-base voltage 10 v i c collector current 100 ma p c collector power dissipation 200 mw t j junction temperature 150 c p d power dissipation t a = 25c (note 1a) 1.5 w t a = 25c (note 1b) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient(mosfet) (note 1a) 86 c/w r ja thermal resistance, junction to ambient(mosfet) (note 1b) 173 device marking device package reel size tape width quantity 143 FDMA1430JP microfet 2x2 7?? 8 mm 5000 units
FDMA1430JP integrated p-channel powertrench ? mosfet and bjt www.fairchildsemi.com 2 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics bjt characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = -250 a, v gs = 0 v -30 v bv dss t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25 c -23 mv/c i dss zero gate voltage drain current v ds = -24 v, v gs = 0 v -1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 1 a v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a-0.4-0.6-1v v gs(th) t j gate to source threshold voltage temperature coefficient i d = -250 a, referenced to 25 c 2.4 mv/c r ds(on) static drain to source on resistance v gs = -4.5 v, i d = -2.9 a 67 90 m v gs = -2.5 v, i d = -2.6 a 81 130 v gs = -1.8 v, i d = -1.7 a 98 170 v gs = -1.5 v, i d = -1 a 114 240 v gs = -4.5 v, i d = -2.9 a, t j = 125 c 102 133 g fs forward transconductance v ds = -5 v, i d = -2.9 a 11 s c iss input capacitance v ds = -15 v, v gs = 0 v, f = 1 mhz 438 580 pf c oss output capacitance 47 70 pf c rss reverse transfer capacitance 41 60 pf t d(on) turn-on delay time v dd = -15 v, i d = -1 a, v gs = -4.5 v, r gen = 6 4.8 10 ns t r rise time 4.4 10 ns t d(off) turn-off delay time 67 107 ns t f fall time 21 33 ns q g total gate charge v dd = -15 v, i d = -2.9 a, v gs = -4.5 v 7.2 10 nc q gs gate to source charge 0.7 nc q gd gate to drain ?miller? charge 1.6 nc v sd source to drain diode forward voltage v gs = 0 v, i s = -1.1 a (note 2) -0.7 -1.2 v t rr reverse recovery time i f = -2.9 a, di/dt = 100 a/ s 16 29 ns q rr reverse recovery charge 5 10 nc i cbo collector cut-off current v cb = 40 v, i e = 0 a 0.1 a h fe dc current gain v ce = 5 v, i c = 5 ma 68 v ce (sat) collector-emitter saturation voltage i c = 10 ma, i b = 0.5 ma 0.3 v f t current gain bandwidth product v ce = 10 v, i c = 5 ma 250 mhz c ob output capacitance v cb = 10 v, i e = 0 a, f = 1 mhz 3.7 pf v i (off) input off voltage v ce = 5 v, i c = 100 a0.5 v v i (on) input on voltage v ce = 0.2 v, i c = 5 ma 1.3 v r1 input resistor 4.7 k r1/r2 resistor ratio 0.1
FDMA1430JP integrated p-channel powertrench ? mosfet and bjt www.fairchildsemi.com 3 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 electrical characteristics notes: 1. r ja is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ja is determined by the user's board design. 2. pulse test : pulse width < 300 us, duty cycle < 2.0% 3. the diode connected between the gate and source serves only as protection against esd. no gate overvoltage rating is implied . 4. guaranteed by icbo 5. guaranteed by iceo . a. 86 c/w when mounted on a 1 in 2 pad of 2 oz copper b. 173 c/w when mounted on a minimum pad of 2 oz copper g df ds sf ss g df ds sf ss
FDMA1430JP integrated p-channel powertrench ? mosfet and bjt www.fairchildsemi.com 4 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 typical characteristics t j = 25 c unless otherwise noted figure 1. 0.00.51.01.52.02.5 0 4 8 12 v gs = -2.5 v v gs = -1.8 v v gs = -3.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = -1.5 v v gs = -4.5 v -i d , drain current (a) -v ds , drain to source voltage (v) on-region characteristics figure 2. 0481 2 0 1 2 3 v gs = -1.8 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance -i d , drain current (a) v gs = -2.5 v v gs = -3.5 v v gs = -1.5 v v gs = -4.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 i d = -2.9 a v gs = -4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 1.01.52.02.53.03.54.04.5 0 100 200 300 400 t j = 125 o c i d = -2.9 a t j = 25 o c -v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0.5 1.0 1.5 2.0 2.5 0 4 8 12 t j = 150 o c v ds = -5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c -i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0.0 0.4 0.8 1.2 0.0001 0.001 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v -i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMA1430JP integrated p-channel powertrench ? mosfet and bjt www.fairchildsemi.com 5 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 figure 7. 02468 0.0 1.5 3.0 4.5 i d = -2.9 a v dd = -20 v v dd = -10 v -v gs , gate to source voltage (v) q g , gate charge (nc) v dd = -15 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 03691215 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 v ds = 0 v t j = 125 o c t j = 25 o c -v gs , gate to source voltage (v) -i g , gate leakage current (a) gate leakage vs gate to source voltage figure 10. 0.1 1 10 100 0.001 0.01 0.1 1 10 50 curve bent to measured data 10 s 100 p s 10 ms dc 1 s 100 ms 1 ms -i d , drain current (a) -v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 173 o c/w t a = 25 o c f o r w a r d b i a s s a f e operating area figure 11. single pul se maximu m power dissipation typical characteristics t j = 25 c unless otherwise noted 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.1 1 10 100 1000 p (pk) , peak transient power (w) single pulse r t ja = 173 o c/w t a = 25 o c t, pulse width (sec)
FDMA1430JP integrated p-channel powertrench ? mosfet and bjt www.fairchildsemi.com 6 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 figure 12. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 173 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
FDMA1430JP integrated p-channel powertrench ? mosfet and bjt www.fairchildsemi.com 7 ?2013 fairchild semiconductor corporation FDMA1430JP rev.c1 dimensional outline and pad layout
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